2. Field of the Invention
This invention relates to RS flip-flops (reset-set type flip-flops), and more particularly to an RS flip-flop having a plurality of set inputs.
2. Description of the Background Art
FIG. 4 is a logic gate diagram showing an ordinary construction of a conventional RS flip-flop. In the drawing, the RS flip-flop has a three-input NOR gate 1 and a two-input NOR gate 2. The three-input NOR gate 1 receives a first set input S1 and a second set input S2 through input terminals 3 and 4. The three-input NOR gate 1 also receives an output of the two-input NOR gate 2. The two-input NOR gate 2 receives a reset input R through an input terminal 5. The two-input NOR gate 2 also receives an output of the three-input NOR gate 1. The outputs of the NOR gates 1 and 2 are applied to output terminals 6 and 7, respectively. Complementary memory state signals or output signals Qand Q ar obtained from the output terminals 6 and 7.
FIG. 5 is a circuit diagram showing the conventional RS flip-flop in greater detail. In the drawing, the three-input NOR gate 1 has p-channel MOS transistors 11-13 and n-channel MOS transistors 14-16. The p-channel MOS transistors 11-13 are connected in series between a power source VDD and an output node N1. The p-channel MOS transistors 11 and 12 receive the set inputs S1 and S2 at the respective gates thereof. The p-channel MOS transistor 13 receives at the gate thereof the output of the two-input NOR gate 2. The n-channel MOS transistors 14-16 are connected in parallel between the output node N1 and ground GND. The n-channel MOS transistors 14 and 15 receive the set inputs S1 and S2 at the respective gates thereof. The n-channel MOS transistor 16 receives at the gate thereof the output of the two-input NOR gate 2. The output node N1 is connected to the output terminal 6.
On the other hand, the two-input NOR gate 2 has p-channel MOS transistors 21 and 22 and n-channel MOS transistors 23 and 24. The p-channel MOS transistors 21 and 22 are connected in series between a power source VDD and an output node N2. The p-channel MOS transistor 21 receives at the gate thereof the output of the three-input NOR gate 1. The p-channel MOS transistor 22 receives at the gate thereof the reset input R. The n-channel MOS transistors 23 and 24 are connected in parallel between the output node N2 and ground GND. The n-channel MOS transistor 23 receives at the gate thereof the output of the three-input NOR gate 1. The n-channel MOS transistor 24 receives at the gate thereof the reset input R. The output node N2 is connected to the output terminal 7.
FIG. 6 is a diagram showing a relationship between input and output of the RS flip-flop shown in FIGS. 4 and 5. An operation of the conventional RS flip-flop will be described with reference to FIG. 6. In the following description, logic "1" corresponds to H level, and logic "0" to L level.
(1) Case of maintaining state of outputs Q and Q:
First, a case will be described in which inputs S1=0, S2=0 and R=0 are applied while the RS flip-flop is outputting Q=1 and Q=0. In this case, the NOR gate 1 receives S1=0, S2=0 and Q=1, whereby the output Qof the NOR gate 1 becomes logic "0". The NOR gate 2 receives R=0 and Q=0, whereby the output Q of the NOR gate 2 becomes logic "1". Thus, the output state will remain unchanged.
Next, a case will be described in which inputs S1=0, S2=0 and R=0 are applied while the RS flip-flop is outputting Q=0 and Q=1. In this case, the NOR gate 1 receives S1=0, S2=0 and Q=0, whereby the output Qof the NOR gate 1 becomes logic "1". The NOR gate 2 receives R=0 and Q=1, whereby the output Q of the NOR gate 2 becomes logic "0". Thus, the output state will remain unchanged.
In this way, the outputs Q and Qmaintain a previous state when the reset input R, set input S1 and set input S2 are all logic "0".
(2) Case of resetting RS flip-flop (Q=0 and Q=1):
First, a case will be described in which inputs S1=0, S2=0 and R=1 are applied when the RS flip-flop is set, i.e. outputting Q=1 and Q=0. In this case, the NOR gate 1 receives S1=0, S2=0 and Q=1, whereby the output Qof the NOR gate 1 becomes logic "1". The NOR gate 2 receives R=1 and Q=0, whereby the output Q of the NOR gate 2 becomes logic "0". Thus, the outputs Q and Qof the RS flip-flop are inverted, which means that the RS flip-flop is reset.
Next, a case will be described in which inputs S1=0, S2=0 and R=1 are applied when the RS flip-flop is reset, i.e. outputting Q=0 and Q=1. In this case, the NOR gate 1 receives S1=0, S2=0 and Q=0, whereby the output Qof the NOR gate 1 becomes logic "1". The NOR gate 2 receives R=1 and Q=1, whereby the output Q of the NOR gate 2 becomes logic "0". Thus, the outputs Q and Qare not inverted and the RS flip-flop maintains the reset state.
(3) Case of setting RS flip-flop (Q=1 and Q=0):
First, a case will be described in which R=0 is inputted and at least one of the set inputs S1 and S2 is changed to logic "1" when the RS flip-flop is set, i.e. outputting Q=1 and Q=0. In this case, the NOR gate 1 receives S1=1, S2=0 and Q=1, or S1=1, S2=1 and Q=1, or S1=0, S2=1 and Q=1, whereby the output Qof the NOR gate 1 becomes logic "0". The NOR gate 2 receives R=0 and Q=0, whereby the output Q of the NOR gate 2 becomes logic "1". Thus, the RS flip-flop maintains the set state.
Next, a case will be described in which R=0 is inputted and at least one of the set inputs S1 and S2 is changed to logic "1"when the RS flip-flop is reset, i.e. outputting Q=0 and Q=1. In this case, the NOR gate 1 receives S1=1, S2=0 and Q=0, or S1=1, S2=1 and Q=0, or S1=0, S2=1 and Q=0, whereby the output Qof the NOR gate 1 becomes logic "0". The NOR gate 2 receives R=0 and Q=0, whereby the output Q of the NOR gate 2 becomes logic "1". Thus, the outputs Q and Qare inverted, which means that the RS flip-flop is set.
The conventional RS flip-flop, as shown in FIG. 5, has many transistors 11-13 connected in series between the power source VDD and output node N1. These transistors 11-13 must all be turned on when inverting the output Qfrom logic "0"to logic "1". However, each of the transistors 11-13 is not turned on immediately upon receipt of an L-level signal at the gate thereof; a predetermined delay time is involved in switching from OFF state to ON state. There occurs a corresponding delay in the change in potential of the output Q. Further, the delay in the potential change of the output Qis passed on to the NOR gate 2 to cause a delay in the potential change of the output Q as well. While the RS flip-flop shown in FIG. 5 has two set inputs, a greater number of set inputs will result in an increase in the number of transistors connected in series between the power source VDD and output node N1, hence a longer delay time.
As described above, the conventional RS flip-flop has the disadvantage of poor response characteristics of the outputs Q and Qto the set inputs and reset input, which is due to the presence of a series circuit of many transistors between the power source and the output terminal. Thus, it has been difficult to employ such conventional RS flip-flops in an electronic circuit required to operate at high speed.